The invention relates generally to a method of forming a pattern of a semiconductor device and, more specifically, to a method of forming a pattern of a semiconductor device which comprises forming a relatively small pattern in comparison with conventional resolution by a double patterning method using an ion implanting process.
Conventional double patterning is typically carried out by one of two methods.
The first method includes twice forming a line/space pattern with a line/space ratio of 1:3, which has a double (2:1) pitch. Since overlay affects the critical dimension (CD) in the first method, it is necessary to accurately regulate overlay in order to secure desirable CD uniformity.
The second method includes forming a line/space pattern with a line/space ratio of 1:3, forming a spacer at a sidewall of the line pattern, and forming a desired pattern using the spacer as a hard mask. Alternatively, the second method includes forming a line/space pattern with a line/space ratio of 1:3, forming a spacer at a sidewall of the line pattern, depositing another material over the spacer, and removing the spacer to obtain a desired pattern. CD regulation is also affected by overlay in this method; when the spacer is not vertical, the etched profile is inferior.